1. Field of the Invention
The present invention pertains to clock phasing or aligning circuits, and more particularly, it pertains to circuitry for aligning data transmitted at a first clock frequency with a second clock running at essentially the same frequency as said first clock but at a differing and undetermined phase relationship.
2. Description of the Prior Art
In data transmission systems it frequently becomes important to rephase data since the phase of a continuous string of data bits will be influenced by the bit pattern being transmitted. This influence is a result of the fact that different data pulse widths received on the transmission line may have slightly different phase shifts. If the clock is carried with the transmitted data -- which is a common practice -- the reformed clock can display a jitter, up to about 10 nanoseconds in some instances, when a varying bit pattern is being received. In a typical system where the data transmitted clock is repeatedly reformed between separate data links, the cumulative jitter on the clock output of the system can have serious effects on the integrity of the data. Thus, it is frequently desirable to shift the data at the end of each data link of a transmission system to a new clock running at generally the same frequency as the clock which shifts the received data to thereby provide a "clean" clock to shift the data over the next data link.
In prior art data handling systems wherein serial data is to be shifted between one clock and another clock, the problem is usually handled through the use of a memory or storage means, such as a shift register. Thus, the incoming data can be shifted into the storage means by the received clock and then shifted out of the storage register by the new clock. This is the conventional approach to the clock phasing problem, and it has a significant advantage in its simplicity. However, it also has some significant disadvantages. For example, such clock phasing circuitry generally requires a large storage capacity thereby increasing the required hardware. Secondly, there is inherently a transmission delay created by the necessity of storing the incoming data, and this may seriously affect the usability of the transmission system. Finally, the necessity for a fixed storage capacity places a limitation on the data capacity of the system since, as will be obvious, individual data words or bit groups which overrun the storage capacity could not be successfully handled by such systems.
If, on the other hand, one attempts to handle serial data bit-by-bit through a logic gate to rephase it with a new clock, any drift, i.e., minor differences in frequency, between the clock received with the incoming data and the new clock will affect the data integrity. Also, differences in phase production due to line dispersion in the incoming data will also affect the data integrity.
One other method which can be used in rephasing data is to directly drive the new clock with an external signal provided by the clock carried by the original data. Thus, a so-called phase locked loop system is formed wherein all of the data in the loop is synchronized to a common clock. In such a system, however, the second clock means must be an oscillator that can be synchronized to an external signal, and thus the second clock is, of necessity, one with a highly variable frequency shift which makes it inapplicable for use at higher frequencies. Thus, the phase locked loop system of providing synchronized data control is generally limited to operation at low frequencies where clock drift will not destroy the integrity of the data.